Time synthesis for power optimization of high performance circuits

ABSTRACT

A system and computer implemented method of modifying characteristics of a circuit provide enhanced performance. One embodiment of the method provides for determining a set of objective parameters for the circuit and receiving noise constraints for the circuit. Values of the objective parameters are optimized based on the noise constraints. By using noise constraints in the optimization process, a number of performance issues can be addressed.

BACKGROUND OF THE INVENTION

[0001] 1. Technical Field

[0002] The present invention generally relates to integrated circuitdesign. More particularly, the invention relates to a computerimplemented method of modifying circuit characteristics that involvesnoise and power optimization.

[0003] 2. Discussion

[0004] 2. Integrated circuit (IC) design is a critical component to thedevelopment of personal computers (PCs), personal digital assistance(PDAs), wireless communication devices and many other systems. In orderto achieve the desired functionality and speed, logic of varyingcomplexity must often be developed for the IC. In the past, standardlogic has been executed by complementary metal-oxide semiconductor(CMOS) circuitry, which is well documented and widely used in industry.More complex, high speed logic has used domino circuits, which includeboth dynamic and static gates. Domino circuitry is described in a numberof sources as U.S. Pat. No. 6,275,071 to Ye et al.

[0005] It has been determined that a number of tradeoffs must be madewhen developing high speed circuits such as domino circuits. Forexample, power consumption is a particular parameter that is often atodds with timing constraints. As a general matter, in order to reducedelays, more robust, power consuming gates must be used. Other tradeoffsrelate to noise reduction and real estate minimization.

[0006] Conventional approaches to modifying given circuitcharacteristics in accordance with the above-described tradeoffs involvedetermining a set of objective parameters such as available device sizesand power levels, and obtaining various constraints for the circuit.Typically, timing constraints and physical constraints are often used toprovide practical limits on the reduction of power levels and realestate usage. Thus, signals must arrive “on time”, gates cannot besmaller than realistically possible, and the values of the objectiveparameters are optimized with these constraints in mind. While theabove-described approach has been acceptable under certaincircumstances, the increasing complexity of more recent logicarchitectures has brought to light a number of difficulties to beaddressed.

[0007] A particular difficulty relates to noise. A major source of noisein an IC is capacitative and inductive coupling between two or moresignal paths, and is often characterized as “crosstalk”. Although noisecoupling can have profound effects on timing and power considerations,and can lead to functional failure in domino logic, conventionalapproaches to circuit optimization often do not take into account theseeffects.

[0008] Another concern with regard to IC design is the manner in whichtraditional technologies approach the actual optimization. For example,earlier designs worked with only one path at a time, rather thanperforming a simultaneous solution of tradeoffs in sizing across amulti-output block. It has been determined that such path-wiseoptimization methods can exhibit unreliable convergence even if marginsand interaction with place-and-route is neglected. While certainattempts have been made at simultaneous optimization, the inability toconsider noise constraints limits their practical usefulness.Furthermore, these approaches do not include a mechanism for employingrealistic gate delay models, especially if these models are non-convexand discrete.

[0009] Additionally, reported methods do not describe a mechanism forleveraging the cost-function information from the results of anoptimization step. Such a mechanism would enable re-synthesis ofnetlists in order to improve power versus delay optimization.Conventional methods also do not show wiring/shielding directives andpower-cost sensitivities being used to facilitate convergence with logicsynthesis and place-and-route operations. Furthermore, designer orproject input templates cannot adequately be used to configure andcontrol the optimization and synthesis processes. In addition, manyconventional methods of modifying circuit characteristics do notdemonstrate the ability to optimize a mix of fixed and continuouslytunable gates.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The various advantages of the present invention will becomeapparent to one skilled in the art by reading the followingspecification and appended claims, and by referencing the followingdrawings, in which:

[0011]FIG. 1 is a flowchart of an example of a computer implementedmethod of modifying circuit characteristics in accordance with oneembodiment of the present invention;

[0012]FIG. 2 is a flowchart of an example of a computer implementedmethod of optimizing objective parameter values in accordance with oneembodiment of the present invention;

[0013]FIG. 3 is a flowchart of an example of a process for developingsensitivity factors in accordance with one embodiment with the presentinvention;

[0014]FIG. 4 is a diagram illustrating an example of a set of objectiveparameters in accordance with one embodiment of the present invention;

[0015]FIG. 5 is a flowchart of an example of a process for minimizingpower costs to a circuit in accordance of one embodiment of the presentinvention;

[0016]FIG. 6 is a block diagram showing an example of a dual-nestedoptimization approach in accordance with one embodiment of the presentinvention; and

[0017]FIG. 7 is a detailed diagram of an example of timed synthesis flowin accordance of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] A system and computer implemented method of modifyingcharacteristics of a circuit provide enhanced performance. Oneembodiment of the method provides for determining a set of objectiveparameters for the circuit and receiving noise constraints for thecircuit. Values of the objective parameters are optimized based on thenoise constraints. By using noise constraints in the optimizationprocess, a number of performance issues can be addressed.

[0019] Further in accordance with an embodiment of the presentinvention, a computer implemented method of optimizing objectiveparameter values is provided. A set of sensitivity factors is developedbased on the objective parameters and noise margins in accordance withnoise constraints for the circuits such that the sensitivity factorscharacterize a noise sensitivity of the circuit. Objective parametervalues and modified noise margins are selected based on the sensitivityfactors such that the objective parameter values minimize power costs tothe circuit. The method further provides for repeating the developingand selecting until changes in the objective parameter values fall belowa predetermined threshold.

[0020] In another aspect of the invention, a computer-readable storagemedium stores a set of instructions, where the set of instructions arecapable of being executed by a processor to form a method of optimizingvalues of objective parameters for a circuit.

[0021] It is to be understood that both the foregoing generaldescription and the following detailed description are merely exemplaryof the invention, and are intended to provide an overview or frameworkfor understanding the nature and character of the invention as it isclaimed. The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and of theinvention, and together with the description serve to explain theprinciples and operation of the invention.

[0022]FIG. 1 shows a computer implemented method 20 of modifyingcharacteristics 22 of a circuit (not shown). The circuit can be any typeof integrated circuit, although the examples discussed herein willprimarily refer to computer processors. The format of the circuitcharacteristics 22 may also vary depending on the application, but ispreferably a netlist, which can be generated by any number ofcommercially available software packages. Netlists are widely understoodin the industry, as apparent from the discussion in U.S. Pat. No.6,289,491 to Dupenloup.

[0023] It can be seen that the method 20 generally provides fordetermining a set of objective parameters 24 for the circuit atprocessing block 26. As will be discussed in greater detail below,objective parameters 24 primarily relate to power consumption and therelationship can be either direct or indirect. For example, device powerlevels directly define the power costs associated with a given device,whereas device sizing indirectly defines power costs. The objectiveparameters 24 include such power related components, where theparameters 24 can take on power level and sizing values in accordancewith various constraints, user-defined inputs and optimizationdirectives. It can further be seen that block 28 provides for receivingnoise constraints 30 for the circuit. Timing constraints 32 and physicalconstraints 33 are also obtained in accordance with other establishedprinciples and techniques. Values of the objective parameters 24 areoptimized at block 34 based on the noise constraints 30 and the resultis a modified circuit characteristics 36 with optimized objectiveparameter values.

[0024] It will be appreciated that the modified circuit characteristics36 provides a unique solution to the difficult problem of power versusdelay optimization in high speed circuits. The method 20 is used inconjunction with a larger system that includes library generation, logicsynthesis, place-and-route, and physical compilation, and improvesdesign productivity. As will be discussed in greater detail below, themethod 20 provides shorter turn-around times for initial design,engineering change orders and other design processes. It should be notedthat the method 20 is applicable to control applications as well asdatapath applications and has been tested in both cases. Adaptation isprovided to multiple types of circuit technologies and clocking methods.

[0025] Turning now to FIG. 2, the preferred approach to optimizingobjective parameter values 44 is shown in greater detail at block 34.Specifically, it can be seen that a set of sensitivity factors 40 isdeveloped at block 38 based on the objective parameters 24 and noisemargins 42 in accordance with the noise constraints 30. The sensitivityfactors 40 therefore characterize a noise sensitivity of the circuit. Itshould be noted that timing constraints 32 and physical constraints 33(FIG. are also used in the sensitivity factor development process.Objective parameter values 44 and modified noise margins 42 are selectedat block 46 based on the sensitivity factors 40 such that the objectiveparameter values 44 minimize power costs to the circuit. Processingblock 48 provides for repeating the developing and selecting untilchanges in the objective parameter values 44 fall below a predeterminedthreshold. The sensitivity factors 40 therefore provide a uniqueapproach to circuit optimization that enables the use of noiseconstraints 30 to iteratively apply noise margins 42 to the nodes of thecircuit.

[0026] Turning now to FIG. 3, the preferred approach to developingsensitivity factors is shown in greater detail at block 38.Specifically, block 50 provides for allocating initial noise margins toa plurality of nodes in the circuit. Initial objective parameter valuesare set at block 52 in accordance with the initial noise margins. It canfurther be seen that blocks 54 and 56 provide for repeating theallocating and setting for varied noise margins. In particular, FIGS. 3and 4 illustrate that discrete components 24 a of the objectiveparameters can be selected such that the objective parameter valuesdefine dynamic logic settings. As best shown in FIG. 4, one or moredynamic logic families can be selected, where each dynamic logic familyhas dynamic gates with corresponding transistor widths and power levels.In addition to discrete components, continuously tunable components 24 bof the objective parameters can be selected such that the objectiveparameters define static logic settings. One or more static logic gatesmay be selected where each static logic gate has corresponding widthsand power levels. By partitioning the objective parameter valueselection based on the tunability of the selected component, a morerobust optimization system is achieved. This is particularly true withregard to high performance logic circuits such as domino circuits.

[0027] Returning now to FIG. 3, it can further be seen that during eachpass, power costs to the full cone of logic behind each node in thecircuit are measured at processing block 58. In addition, power costs tothe full cone of logic ahead of each node in the circuit are calculatedat block 60. These calculations and measurements are stored in anacceptable computer-readable memory (not shown) for summarization atblock 62. Thus, by summarizing the measured and calculated power costsinto a common sensitivity parameter custom-class results can be obtainedwith very little manual tuning.

[0028] Turning now to FIG. 5, the preferred approach to selectingobjective parameter values 44 and modified noise margins is shown ingreater detail at block 46. Specifically, it can be seen that anobjective function 66 is constructed at block 64 based on thesensitivity factors 40. The objective function 66 is sent to a linearprogram (LP) solver such that the LP solver generates the objectiveparameter values 44 and the noise margins 42. LP solvers have been welldocumented and are commercially available from a number of sources.

[0029]FIG. 6 shows the key elements of the timed synthesis flow ingreater detail. Generally, processing blocks 38′, 46′ and 68 definethree phases of the overall synthesis flow. In particular, processingblock 38′ provides for sizing and analysis, and block 46′ provides forformulation of the objective function and revised constraints.Furthermore, block 68 provides for network re-synthesis and criticalpath analysis. Each of these phases will now be addressed in detail.

[0030] Sizing and Analysis—Phase One

[0031] Sizing and analysis is performed by analyzing the circuittopology and timing relative to block and technology file requirements.In particular, failures to meet limits such as maximum capacitances(CMAX), transition time (TT) targets, capacitive loading on inputs (CIN)or excesses on thresholds for fan-out or fan-in or capacitive loading onclocks are identified. These are input as penalty functions to theoptimization phase. It should be noted that, standard timing analysisengines may be used for this step. The engine should be well calibratedwith respect to the final verification engine and is preferably the sameone. Furthermore, a noise constraint space is derived for all cells inthe library. It is preferred that the library characterization isexpressed as a polynomial function.

[0032] Once the circuit topology and timing is analyzed, the circuit issized to meet minimum and maximum delay targets and noise targets,working from outputs to inputs, using given library characterizationdata and given targets. In particular, first pass sizing uses defaulttargets given by the designer, project, or library, in combination withthe environmental information (EVR) for the functional block (FUB) and awire load model. In addition, delay targets after the first pass arefedback from the optimization phase; and the sizing module uses librarycharacterization information for maximum delays, minimum delays,relative to hold time, contention, and other requirements as given byproject or designer template inputs. The sizing module also uses librarycharacterization information, if available, as a function of fan-outcharacteristics, such as ratio of coupling capacitance to totalcapacitance, total capacitance, resistance values, and worst case inputnoise margin of a receiving gate in the fan-out. The preferred approachis to extrapolate beyond any given maximum values. Furthermore, ifmaximum power levels or device sizes in the library are exceeded inorder to get the delay, then the result is extrapolated for parallelre-powered gates. As already discussed, phase three re-synthesis willforce the meeting of any constraints that are exceeded during the sizingand optimization phases.

[0033] It can further be seen that perturb delays are multiplied inpositive and negative directions and a re-sizing is executed. Nodalpower/delay sensitivities and bounds on sensitivities are calculatedbased on the results, and re-calculated on every pass. In particular,the costs of logic under the cone of influence of each node areincluded; and each sizing perturbation step includes the above sizingwith respect to margins. It should be noted that standard dynamicstep-size techniques are applicable, where the step size for each passis a function of the trajectory and rate-of-change of the prior results.Furthermore, bounds on the sensitivities are also determined by defaultas a function (e.g. 2×) of step-size or by designer over-ride.

[0034] Phase one further provides for testing for escape from iterationaccording to whether changes in timing penalties or sizing result aresmall. Specifically, the change threshold for escape is set either bydefault, project, setup, or a designer over-ride. It can be seen that ifa small sizing change is found, but cost thresholds or timing penaltythresholds are exceeded, the synthesis flow proceeds to design phasethree for network re-synthesis. Furthermore, if the stopping criteriaare met, phase one outputs a netlist, sensitivity parameters, timinganalysis results, and results from the previous phase three pass forcritical path analysis and wire re-design directives. This informationcan be vital to getting custom-class results in convergence withplace-and-route optimization and with logic synthesis.

[0035] It should be noted that wiring input 80 such as wire data withcoupling or wire load models can be provided to processing block 38′ toassist in the analysis of delays, noise and topologies.

[0036] Obiective Function and Constraint Formulation—Phase Two

[0037] The objective function is formed based on the above calculatedsensitivity and penalty parameters and the total power-cost of theblock, and the optimization variable is delay. Bounds for delay and fortransition times for each node are formed from template inputs and fromtiming-analysis/EVR results and from the range set for the sensitivity.In general, the sensitivity range is the most constraining bound. Allbounds are re-formed on each pass.

[0038] The LP solver outputs a set of nodal delays that are exactlyoptimal with respect to the given parameters and bounds. In particular,it should be noted that although the LP solver always returns a result,the result may exceed some bounds. Furthermore, the LP solver is astandard product, which has seen many advances by vendors and academia.The best available in these products and techniques can be leveragedbased on the given application.

[0039] As already discussed, optimized delays are fed back to the phaseone modules for analysis and sizing. The iteration continues untilstopping criteria are met following analysis in phase one. Furthermore,processing block 46′ illustrates that both minimum and maximum delaysare found. In this regard, it should be noted that conventionalapproaches fail to determine minimum delays when constructing timingmargins.

[0040] Network Re-synthesis and Critical Path Analysis—Phase Three

[0041] The phase three module analyzes the topological graph to find thehighest pathwise cost and penalty totals. Generally, the modifiedcircuit characteristics 36′, includes the optimized parameter values,which are used in the critical paths. Thus, block 68 further providesfor correcting the objective parameters 24′ and noise constraints, whichare included in the designer input 70, for topological costs that areabove a predetermined level. Iteration loop 72 provides for repeatingthe optimizing with the corrected objective parameters and noiseconstraints. Specifically, block 68 provides for splitting nets, mergingnets, adding buffers, and substituting cells in the circuit with librarycells, where the library cells have extended noise characteristics. Theresult is a modified netlist 74, which is sized to meet block delaytargets with minimized power costs and with correct margins.Additionally, node sensitivities 76 can be used in logic synthesis orplace and route optimization. It can further be seen that physical data78 such as wire sizes and shielding directives can be also provided forplace-and-route operations.

[0042] In particular, final analysis results are output for use by logicsynthesis if the designer elects logic synthesis re-structuring ortransforms, such as phase optimization, critical path extraction andre-minimization, or mapping to a difference library. Furthermore, nodesthat have exceed library or template maximums for power levels, noise,or other characterization parameters are found.

[0043] For fan-outs greater than one (or some other given threshold),phase three splits the fan-out on nodes with exceeded maximums anddistributes the loads represented by the receivers according to thepathwise cost information. In particular paths that are less criticalare separated from more critical paths during this step; delays on thesepaths are reset to the maximum value for upsizing only as much asnecessary in the net sizing and optimization phases. Furthermore, netsplitting can be invoked by directives from place-and-route in order toreduce congestion caused by high fan-out nodes. In this regard, itshould be noted that high fan-out nodes occur more frequently in highspeed logic with aggressively flattened levels.

[0044] For fan-outs of one or less than some other given threshold, abuffering stage is added, according to the given template or rules-setfor available buffers and the type of nodes on which they can be used.In dynamic logic, whether inverting or non-inverting buffers, orstate-storage buffers need be used is a function of the type of node. Inparticular, if maximums are exceeded due to noise on low-fan-out nodes,phase three provides for the addition of shielding or the reduction ofwire lengths. It is preferred that the list of these changes becomesdirectives to next pass of place-and-route.

[0045] For excessive penalty functions due to delays that are too fast(min-delays), buffering is added according to the given template orrules set for available buffers and the type of node on which they canbe used. It should be noted that designer over-rides are supported onall of the above functions.

[0046] Turning now to FIG. 7, a detailed data flow of the preferredtimed synthesis is shown. Generally, a FUB-specific flow control scriptor graphical user interface (GUI) 82 manages the optimization process.Designer input 70 can include a number of types of information. Forexample, flow overrides 70 a, timing overrides 70 b, wire load overrides70 c, sensitivity delta and range 70 d, objective parameter overrides 70e, and library net overrides 70 f are all useful in the optimizationprocess. Non-block-specific files are shown generally at 84. Atopological analysis module 86 uses wiring input 80 and netlist 22′ togenerate timing results 88 based on script output 92 a from GUI 82 andother iterative data. Specifically, sizing iterative data 94 is used fornoise and delays. An allocation module 90 allocates node delays based onscript output 92 b from the GUI 82, penalty parameters 96, and data fromthe topological analysis module 86.

[0047] A sizing module 98 generates an optimized, sized netlist 36″based on the penalty parameters 96, GUI script output 92 c, and variousother data as shown in FIG. 7. In particular, LP iterative data 100 isused to size gate power levels or device widths. It can further be seenthat a sensitivity module 102 uses GUI script output 92 d and a widevariety of data to generate node delays and power sensitivities 104. Inaddition, GUI script output 92e feeds a bounding module 106, while GUIscript output 92 f feeds the LP solver 108. As already discussed, acritical path module 110 can use GUI script output 92 g to generateinput/output (I/O) and clock criticalities 112. Shielding directives 114result from re-synthesis module 116, which uses GUI script output 92 h.

[0048] Those skilled in the art can now appreciate from the foregoingdescription that the broad teachings of the present invention can beimplemented in a variety of forms. Therefore, while this invention hasbeen described in connection with particular examples thereof, the truescope of the invention should not be so limited since othermodifications will become apparent to the skilled practitioner upon astudy of the drawings, specification, and following claims.

We claim:
 1. A computer implemented method of modifying characteristicsof a circuit, the method comprising: determining a set of objectiveparameters for the circuit; receiving noise constraints for the circuit;and optimizing values of the objective parameters based on the noiseconstraints.
 2. The method of claim 1 further including: developing aset of sensitivity factors based on the objective parameters and noisemargins in accordance with the noise constraints such that thesensitivity factors characterize a noise sensitivity of the circuit;selecting objective parameter values and modified noise margins based onthe sensitivity factors such that the objective parameter valuesminimize power costs to the circuit; and repeating the developing andselecting until changes in the objective parameter values fall below apredetermined threshold.
 3. The method of claim 2 further including:allocating initial noise margins to a plurality of nodes in the circuit;setting initial objective parameter values in accordance with theinitial noise margins; and repeating the allocating and setting forvaried noise margins.
 4. The method of claim 3 further includingselecting discrete components of the objective parameters such that theobjective parameter values define dynamic logic settings.
 5. The methodof claim 4 further including selecting one or more dynamic logicfamilies, each dynamic logic family having dynamic gates withcorresponding transistor widths and power levels.
 6. The method of claim3 further including selecting continuously tunable components of theobjective parameters such that the objective parameter values definestatic logic settings.
 7. The method of claim 6 further includingselecting one or more static logic gates, each static logic gate havingcorresponding widths and power levels.
 8. The method of claim 2 furtherincluding: measuring power costs to a full cone of logic behind eachnode in the circuit; calculating power costs to a full cone of logicahead of each node in the circuit; summarizing the measured andcalculated power costs into a common sensitivity parameter.
 9. Themethod of claim 2 further including: constructing an objective functionbased on the sensitivity factors; and inputting the objective functionto a linear program solver such that the linear program solver generatesthe objective parameter values and the noise margins.
 10. The method ofclaim 1 further including: receiving timing constraints for the circuit;and optimizing the objective parameter values based on the timingconstraints.
 11. The method of claim 10 further including: determiningtiming margins in accordance with the timing constraints; said timingmargins including minimum and maximum delays for a plurality of nodes inthe circuit.
 12. The method of claim 1 further including: receivingphysical constraints for the circuit; and optimizing the objectiveparameter values based on the physical constraints.
 13. The method ofclaim 1 further including: conducting a topological analysis on criticalpaths of the circuit, where the optimized objective parameter values areused in the critical paths; correcting the objective parameters andnoise constraints for topological costs that are above a predeterminedlevel; and repeating the optimizing with the corrected objectiveparameters and noise constraints.
 14. The method of claim 13 furtherincluding splitting nets in the circuit.
 15. The method of claim 13further including merging nets in the circuit.
 16. The method of claim13 further including adding buffers to the circuit.
 17. The method ofclaim 13 further including substituting cells in the circuit withlibrary cells where the library cells have extended noisecharacteristics.
 18. A computer implemented method of optimizing valuesof objective parameters for a circuit, the method comprising: developinga set of sensitivity factors based on the objective parameters and noisemargins in accordance with noise constraints for the circuit such thatthe sensitivity factors characterize a noise sensitivity of the circuit;selecting objective parameter values and modified noise margins based onthe sensitivity factors such that the objective parameter valuesminimize power costs to the circuit; and repeating the developing andselecting until changes in the objective parameter values fall below apredetermined threshold.
 19. The method of claim 18 further including:allocating initial noise margins to a plurality of nodes in the circuit;setting initial objective parameter values in accordance with theinitial noise margins; and repeating the allocating and setting foradjusted noise margins.
 20. The method of claim 19 further includingselecting discrete components of the objective parameters such that theobjective parameter values define dynamic logic settings.
 21. The methodof claim 20 further including selecting one or more dynamic logicfamilies, each dynamic logic family having dynamic gates withcorresponding transistor widths and power levels.
 22. The method ofclaim 19 further including selecting continuously tunable components ofthe objective parameters such that the objective parameter values definestatic logic settings.
 23. The method of claim 22 further includingselecting one or more static logic gates, each static logic gate havingcorresponding widths and power levels.
 24. A computer-readable storagemedium storing a set of instructions, the set of instructions capable ofbeing executed by a processor to perform a method of optimizing valuesof objective parameters for a circuit, the method comprising: developinga set of sensitivity factors based on the objective parameters and noisemargins in accordance with noise constraints for the circuit such thatthe sensitivity factors characterize a noise sensitivity of the circuit;selecting objective parameter values and modified noise margins based onthe sensitivity factors such that the objective parameter valuesminimize power costs to the circuit; and repeating the developing andselecting until changes in the objective parameter values fall below apredetermined threshold.
 25. The medium of claim 24 wherein the methodfurther includes: allocating initial noise margins to a plurality ofnodes in the circuit; setting initial objective parameter values inaccordance with the initial noise margins; and repeating the allocatingand setting for adjusted noise margins.
 26. The medium of claim 25wherein the method further includes selecting discrete components of theobjective parameters such that the objective parameter values definedynamic logic settings.
 27. The medium of claim 25 wherein the methodfurther includes selecting continuously tunable components of theobjective parameters such that the objective parameter values definestatic logic settings.